In modern communications circuitry, digital phase-locked loops (DPLL's) are used to generate signals of arbitrary frequency by phase locking to a reference signal having a known frequency. To digitally compare the phase of a DPLL output signal with the phase of a reference signal, the DPLL may employ a mixed-signal block known as an accumulated phase-to-digital converter (APDC). The APDC generates a digital representation of an accumulated phase of the DPLL output signal.
In conventional DPLL's, an APDC may be implemented using a counter combined with a time-to-digital converter (TDC). The counter may count the integer portion of the accumulated output signal phase in cycles of the output signal, while the TDC may measure the fractional portion of the accumulated output signal phase. The counter and TDC outputs may be combined to produce the total accumulated output signal phase.
For DPLL's that generate high-frequency output signals, the counter and TDC may both be required to operate at correspondingly high frequencies. For example, the counter is required to count the total number of elapsed cycles at the frequency of the output signal, while the buffers in a delay line of the TDC may also be required to switch at the frequency of the output signal. High-frequency operation of DPLL component circuitry generally leads to higher power consumption by the DPLL. Furthermore, to match a fractional portion of the accumulated output signal phase with the corresponding integer portion, the signal path delays in the counter and TDC should be precisely matched. This requirement further complicates the design of APDC's.
It would be desirable to provide a novel APDC that offers both improved power efficiency and ease of design over prior art APDC's.